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Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
CDK2308
Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
FEATURES
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General Description
The CDK2308 is a high performance, low power dual Analog-to-Digital Converters (ADC). The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range. Several idle modes with fast startup times exist. Each channel can independently be powered down and the entire chip can either be put in Standby Mode or Power Down mode. The different modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. The CDK2308 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave and CMOS clock inputs.
10-bit resolution 20/40/65/80MSPS maximum sampling rate Ultra-low power dissipation: 24/43/65/78mW 61.6dB SNR at 80MSPS and 8MHz FIN Internal reference circuitry 1.8V core supply voltage 1.7V - 3.6V I/O supply voltage Parallel CMOS output 64-pin QFN package (TQFP-64 package option also available) Dual channel Pin compatible with CDK2307
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APPLICATIONS
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Medical Imaging Portable Test Equipment IF Communication Digital Oscilloscopes
Functional Block Diagram
CLKN CLK_EXT
10
10
Ordering Information
Part Number CDK2308AILP64 CDK2308BILP64 CDK2308CILP64 CDK2308DILP64 CDK2308AITQ64 CDK2308BITQ64 CDK2308CITQ64 CDK2308DITQ64 Speed 20MSPS 40MSPS 65MSPS 80MSPS 20MSPS 40MSPS 65MSPS 80MSPS Package QFN-64 QFN-64 QFN-64 QFN-64 TQFP-64 TQFP-64 TQFP-64 TQFP-64 Pb-Free Yes Yes Yes Yes Yes Yes Yes Yes RoHS Compliant Yes Yes Yes Yes Yes Yes Yes Yes Operating Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Packaging Method Tray Tray Tray Tray Tray Tray Tray Tray
CLKP
Rev 2B
Moisture sensitivity level for all parts is MSL-2A. Preliminary (c)2009 CADEKA Microcircuits LLC www.cadeka.com
Data Sheet
Pin Configuration QFN-64, TQFP-64
D0_5 D0_4 D0_3
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
1 2 3 4 5 6 7 8 9 10 11 12
DVSSCLK DVDDCLK CLKP CLKN
49
48 47 46 45 44 N/C N/C N/C
CLK_EXT
QFN-64,TQFP-64
CDK2308
43 42 41 40 39 38 37 36 35 34 33
13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
N/C
N/C
Pin Assignments
Pin No. 1, 18, 23 2 3, 9, 12 4, 5, 8 6, 7 10, 11 13 14 15 16 17, 64 19 20 21 22 24, 41, 58 25, 40, 57 Pin Name DVDD CM_EXT AVDD AVSS IP0, IN0 IP1, IN1 DVSSCLK DVDDCLK CLKP CLKN DVSS CLK_EXT_EN DFRMT PD_N OE_N_1 OVDD OVSS Description Digital and I/O-ring pre driver supply voltage, 1.8V Common Mode voltage output Analog supply voltage, 1.8V Analog ground Analog input Channel 0 (non-inverting, inverting) Analog input Channel 1 (non-inverting, inverting) Clock circuitry ground Clock circuitry supply voltage, 1.8V Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave) Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground Digital circuitry ground CLK_EXT signal enabled when low (zero). Tristate when high. Data format selection. 0: Offset Binary, 1: Two's Complement Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up, always apply Power Down mode before using Active mode to reset chip. Output Enable Channel 1. Tristate when high I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V. Ground for I/O ring
CLK_EXT_EN
N/C
Rev 2B
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Data Sheet
Pin Assignments (Continued)
Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 59 60, 61 Pin Name NC NC NC D1_0 D1_1 D1_2 D1_3 D1_4 D1_5 D1_6 D1_7 D1_8 D1_9 ORNG_1 CLK_EXT NC NC NC D0_0 D0_1 D0_2 D0_3 D0_4 D0_5 D0_6 D0_7 D0_8 D0_9 ORNG_0 OE_N_0 CM_EXTBC_1, CM_EXTBC_0 SLP_N_1, SLP_N_0 Description No Connect No Connect
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
No Connect Output Data Channel 1 (LSB) Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 Output Data Channel 1 (MSB) Out of Range flag Channel 1. High when input signal is out of range Output clock signal for data synchronization. CMOS levels. No Connect No Connect No Connect Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 Output Data Channel 0 (MSB) Out of Range flag Channel 0. High when input signal is out of range. Output Enable Channel 0. Tristate when low. Bias control bits for the buffer driving pin CM_EXT 00: Off 01: 50uA 10: 500uA 11: 1mA Sleep Mode 00: Sleep Mode 10: Channel 1 active 01: Channel 0 active 11: Both channels active
Rev 2B
62, 63
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3
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots.
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
Parameter AVDD, AVSS DVDD, DVSS AVSS, DVSSCK, DVSS, OVSS OVDD, OVSS CKP, CKN, DVSSCK Analog inputs and outpts (IPx, INx, AVSS) Digital inputs Digital outputs
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
Max +2.3 +2.3 +0.3 +3.9 +3.9 +2.3 +3.9 +3.9
Unit V V V V V V V V
Reliability Information
Parameter Storage Temperature Range Lead Temperature (Soldering, 10s) Min -60 J-STD-020 Typ Max +150 Unit C
ESD Protection
Product Human Body Model (HBM) TQFP-64, QFN-64 2kV
Recommended Operating Conditions
Parameter Operating Temperature Range Min -40 Typ Max +85 Unit C
Rev 2B
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Data Sheet
Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
DC Accuracy
Parameter
No Missing Codes Offset Error Gain Error Gain Matching
Conditions
Min
Typ
Guaranteed
Max
Units
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
Midscale offset Full scale range deviation from typical Gain matching between channels 12-bit level 12-bit level -6
1 6 0.05 0.15 0.2 VAVDD/2
LSB %FS %FS LSB LSB V VCM +0.2 V Vpp pF MHz
DNL ILE VCMO
Differential Non-Linearity Integral Non-Linearity Common Mode Voltage Output Input Common Mode Full Scale Range Input Capacitance Bandwidth
Analog Input
VCMI VFSR Analog input common mode voltage Differential input voltage range Differential input capacitance Input bandwidth, full power Supply voltage to all 1.8V domain pins. See Pin Configuration and Description Output driver supply voltage (OVDD). Must be higher than or equal to Core Supply Voltage (VOVDD VOCVDD) 500 1.7 1.7 1.8 2.5 2 3.6 VCM -0.1 2 2
Power Supply
AVDD, DVDD OVDD Core Supply Voltage I/O Supply Voltage V V
Rev 2B
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Data Sheet
Electrical Characteristics - CDK2308A
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Performance
Parameter
Conditions
FIN = 2MHz
Min
Typ
61.7
Max
Units
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBc
SNR
Signal to Noise Ratio
FIN = 8MHz FIN FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 20MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 20MHz Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz
60
61.6 61.6 61.6 61.7
SNDR
Signal to Noise and Distortion Ratio
60
61.6 60.5 61.6 80
SFDR
Spurious Free Dynamic Range
70
81 70 80 -90
HD2
Second order Harmonic Distortion
-80
-90 -90 -90 -80
HD3
Third order Harmonic Distortion
-70
-81 -70 -80 10
ENOB
Effective number of Bits
9.7
9.9 9.8 9.9 -105
XTALK
Crosstalk
Power Supply
AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode one channel Power Dissipation, Sleep mode both channels 20 15 8.2 1.7 2.8 2.3 14.8 8.8 23.6 9.9 15.2 7.7 mA mA mA mA mW mW mW W mW mW MSPS MSPS
OIDD
Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode 1 Sleep Mode 2
Rev 2B
Clock Inputs
Max. Conversion Rate Min. Conversion Rate
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Data Sheet
Electrical Characteristics - CDK2308B
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Performance
Parameter
Conditions
FIN = 2MHz
Min
Typ
61.6
Max
Units
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBc
SNR
Signal to Noise Ratio
FIN = 8MHz FIN FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 30MHz FIN = 2MHz FIN = 8MHz FIN FS/2 FIN = 30MHz Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz
60
61.6 61.6 61.5 61.6
SNDR
Signal to Noise and Distortion Ratio
60
61.6 61.2 61.4 80
SFDR
Spurious Free Dynamic Range
70
81 72 80 -90
HD2
Second order Harmonic Distortion
-80
-90 -85 -85 -80
HD3
Third order Harmonic Distortion
-70
-81 -72 -80 9.9
ENOB
Effective number of Bits
9.7
9.9 9.9 9.9 -100
XTALK
Crosstalk
Power Supply
AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode one channel Power Dissipation, Sleep mode both channels 40 20 14.4 3.4 5.1 4.2 25.9 16.6 42.5 9.7 25.7 11.3 mA mA mA mA mW mW mW W mW mW MSPS MSPS
OIDD
Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode 1 Sleep Mode 2
Rev 2B
Clock Inputs
Max. Conversion Rate Min. Conversion Rate
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Data Sheet
Electrical Characteristics - CDK2308C
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD=2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Performance
Parameter
Conditions
FIN = 8MHz
Min
60
Typ
61.6 61.6 61.5 61.3
Max
Units
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBc
SNR
Signal to Noise Ratio
FIN = 20MHz FIN FS/2 FIN = 40MHz FIN = 8MHz 60 FIN = 20MHz FIN FS/2 FIN = 40MHz FIN = 8MHz 70 FIN = 20MHz FIN FS/2 FIN = 40MHz FIN = 8MHz -80 FIN = 20MHz FIN FS/2 FIN = 40MHz FIN = 8MHz -70 FIN = 20MHz FIN FS/2 FIN = 40MHz FIN = 8MHz 9.7 FIN = 20MHz FIN FS/2 FIN = 40MHz Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz
61.6 61.6 60.4 61.1 77 77 70 75 -90 -95 -85 -90 -77 -77 -70 -75 9.9 9.9 9.7 9.9 -97
SNDR
Signal to Noise and Distortion Ratio
SFDR
Spurious Free Dynamic Range
HD2
Second order Harmonic Distortion
HD3
Third order Harmonic Distortion
ENOB
Effective number of Bits
XTALK
Crosstalk
Power Supply
AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode one channel Power Dissipation, Sleep mode both channels 65 40 22 5.2 7.9 6.4 39.6 25.4 65 9.3 38.2 15.7 mA mA mA mA mW mW mW W mW mW MSPS MSPS
OIDD
Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode 1 Sleep Mode 2
Rev 2B
Clock Inputs
Max. Conversion Rate Min. Conversion Rate
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8
Data Sheet
Electrical Characteristics - CDK2308D
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Performance
Parameter
Conditions
FIN = 8MHz
Min
60
Typ
61.6 61.2 61.3 61.3
Max
Units
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBc
SNR
Signal to Noise Ratio
FIN = 20MHz FIN = 30MHz FIN FS/2 FIN = 8MHz 60 FIN = 20MHz FIN = 30MHz FIN FS/2 FIN = 8MHz 70 FIN = 20MHz FIN = 30MHz FIN FS/2 FIN = 8MHz -80 FIN = 20MHz FIN = 30MHz FIN FS/2 FIN = 8MHz -70 FIN = 20MHz FIN = 30MHz FIN FS/2 FIN = 8MHz 9.7 FIN = 20MHz FIN = 30MHz FIN FS/2 Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz
61.3 60.7 61 59 75 75 75 65 -90 -95 -90 -80 -75 -75 -75 -65 9.9 9.8 9.8 9.5 -95
SNDR
Signal to Noise and Distortion Ratio
SFDR
Spurious Free Dynamic Range
HD2
Second order Harmonic Distortion
HD3
Third order Harmonic Distortion
ENOB
Effective number of Bits
XTALK
Crosstalk
Power Supply
AIDD DIDD Analog Supply Current Digital Supply Current Digital core supply 2.5V output driver supply, sine wave input, FIN = 1MHz 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Power Dissipation, Sleep mode one channel Power Dissipation, Sleep mode both channels 80 65 26.5 6.1 9.5 7.6 47.7 30 77.7 9.1 46.1 18.3 mA mA mA mA mW mW mW W mW mW MSPS MSPS
OIDD
Output Driver Supply Analog Power Dissipation Digital Power Dissipation Total Power Dissipation Power Down Dissipation Sleep Mode 1 Sleep Mode 2
Rev 2B
Clock Inputs
Max. Conversion Rate Min. Conversion Rate
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Data Sheet
Digital and Timing Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 50 MSPS clock, 50% clock duty cycle, -1 dBFS input signal, 5pF capacitive load, unless otherwise noted)
Symbol
Clock Inputs
Parameter
Duty Cycle Compliance Input Range Input Common Mode Voltage Input Capacitance
Conditions
Min
20
Typ
Max
80
Units
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
% high mVpp Vpp
CMOS, LVDS, LVPECL, Sine Wave Differential input swing Differential input swing, sine wave clock input Keep voltages within ground and voltage of OVDD Differential From Power Down Mode to Active Mode From Sleep Mode to Active Mode 20 1 0.8 <0.5 12 5pF load on output bits Relative to CLK_EXT VOVDD 3.0V VOVDD = 1.7V - 3.0V VOVDD 3.0V VOVDD = 1.7V - 3.0V 2 0.8 * VOVDD 0 0 -10 -10 3 VOVDD-0.1 0.1 Post-driver supply voltage equal to pre-driver supply voltage VOVDD = VOCVDD Post-driver supply voltage above 2.25V (1) 10 5 0.8 0.2 * VOVDD 10 10 4 2 400 1.6 0.3 2 900 VOVDD -0.3
V pF clk cycles clk cycles clk cycles ns ps clk cycles ns ns V V V V A A pF V V pF pF
Timing
TPD TSLP TOVR TAP Start Up Time Active Mode Start Up Time Mode Out Of Range Recovery Time Aperture Delay Aperture Jitter Pipeline Delay Output Delay (see timing diagram) Output Delay (see timing diagram)
RMS
TLAT TD TDC
Logic Inputs
VIH VIL IIH IIL CI High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Leakage Current Input Capacitance High Level Output Voltage Low Level Output Voltage Max Capacitive Load
Logic Outputs
VOH VOL CL
Note: (1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum.
Rev 2B
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Data Sheet
+F1 +F2 + +F0
+F4 +F
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
N-13 N-13
N-12
N-11
N-10
N-9
N-8
CLK_EXT
Figure 1. Timing Diagram
Recommended Usage Analog Input
The analog inputs to the CDK2308 is a switched capacitor track-and-hold amplifier optimized for differential operation. Operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. The CM_EXT pin provides a voltage suitable as common mode voltage reference. The internal buffer for the CM_EXT voltage can be switched off, and driving capabilities can be changed by using the CM_EXTBC control input. Figure 2 shows a simplified drawing of the input network. The signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. A small external resistor (e.g. 22) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. A small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. The resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application.
DC-Coupling
Figure 3 shows a recommended configuration for DCcoupling. Note that the common mode input voltage must be controlled according to specified values. Preferably, the CM_EXT output should be used as a reference to set the common mode voltage. The input amplifier could be inside a companion chip or it could be a dedicated amplifier. Several suitable single ended to differential driver amplifiers exist in the market. The system designer should make sure the specifications of the selected amplifier is adequate for the total system, and that driving capabilities comply with the CDK2308 input specifications.
pF
Rev 2B
Figure 3. DC-Coupled Input Detailed configuration and usage instructions must be found in the documentation of the selected driver.
AC-Coupling
A signal transformer or series capacitors can be used to make an AC-coupled input network. Figure 4 shows a recommended configuration using a transformer. Make sure that a transformer with sufficient linearity is selected,
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Figure 2. Input Configuration
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Data Sheet
and that the bandwidth of the transformer is appropriate. The bandwidth should exceed the sampling rate of the ADC with at least a factor of 10. It is also important to keep phase mismatch between the differential ADC inputs small for good HD2 performance. This type of transformer coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have adequate performance at high frequencies. Magnetic coupling between the transformers and PCB traces may impact channel crosstalk, and must hence be taken into account during PCB layout. If the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the ADC will also travel along this distance. If these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the ADC input. This could reduce the ADC performance. To avoid this effect, the source must effectively terminate the ADC kick-backs, or the traveling distance should be very short. If this problem could not be avoided, the circuit in Figure 6 can be used.
Note that startup time from Sleep Mode and Power Down Mode will be affected by this filter as the time required to charge the series capacitors is dependent on the filter cut-off frequency. If the input signal has a long traveling distance, and the kick-backs from the ADC not are effectively terminated at the signal source, the input network of figure 8 can be used. The configuration in figure 8 is designed to attenuate the kickback from the ADC and to provide an input impedance that looks as resistive as possible for frequencies below Nyquist. Values of the series inductor will however depend on board design and conversion rate. In some instances a shunt capacitor in parallel with the termination resistor (e.g. 33pF) may improve ADC performance further. This capacitor attenuate the ADC kickback even more, and minimize the kicks traveling towards the source. However, the impedance match seen into the transformer becomes worse.
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
1:1
120nH 33
33 RT 47
optional
RT 68
120nH
220
pF
33
33
Figure 4. Transformer-Coupled Input Figure 5 shows AC-coupling using capacitors. Resistors from the CM_EXT output, RCM, should be used to bias the differential input signals to the correct voltage. The series capacitor, CI, form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency.
Figure 6. Alternative Input Network
Clock Input And Jitter Considerations
Typically high-speed ADCs use both clock edges to generate internal timing signals. In the CDK2308 only the rising edge of the clock is used. Hence, input clock duty cycles between 20% and 80% is acceptable. The input clock can be supplied in a variety of formats. The clock pins are AC-coupled internally, and hence a wide common mode voltage range is accepted. Differential clock sources as LVDS, LVPECL or differential sine wave can be connected directly to the input pins. For CMOS inputs, the CLKN pin should be connected to ground, and the CMOS clock signal should be connected to CLKP. For differential sine wave clock input the amplitude must be at least 800mVpp.
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Rev 2B
pF
Figure 5. AC-Coupled Input
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Data Sheet
The quality of the input clock is extremely important for high-speed, high-resolution ADCs. The contribution to SNR from clock jitter with a full scale signal at a given frequency is shown in equation 1. SNRjitter = 20 * log (2
*
* FIN * t)
where FIN is the signal frequency, and t is the total rms jitter measured in seconds. The rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal ADC circuitry. For applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. This can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. It might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. It is of utmost importance to avoid crosstalk between the ADC output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. The jitter performance is improved with reduced rise and fall times of the input clock. Hence, optimum jitter performance is obtained with LVDS or LVPECL clock with fast edges. CMOS and sine wave clock inputs will result in slightly degraded jitter performance. If the clock is generated by other circuitry, it should be retimed with a low jitter master clock as the last operation before it is applied to the ADC clock input.
The CDK2308 employs digital offset correction. This means that the output code will be 4096 with the positive and negative inputs shorted together(zero differential). However, small mismatches in parasitics at the input can cause this to alter slightly. The offset correction also results in possible loss of codes at the edges of the full scale range. With "NO" offset correction, the ADC would clip in one end before the other, in practice resulting in code loss at the opposite end. With the output being centered digitally, the output will clip, and the out of range flags will be set, before max code is reached. When out of range flags are set, the code is forced to all ones for over-range and all zeros for under-range.
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
Data Format Selection
The output data are presented on offset binary form when DFRMT is low (connect to OVSS). Setting DFRMT high (connect to OVDD) results in 2's complement output format. Details are shown in Table 1 on page 14.
Reference Voltages
The reference voltages are internally generated and buffered based on a bandgap voltage reference. No external decoupling is necessary, and the reference voltages are not available externally. This simplifies usage of the ADC since two extremely sensitive pins, otherwise needed, are removed from the interface.
Operational Modes
The operational modes are controlled with the PD_N and SLP_N pins. If PD_N is set low, all other control pins are overridden and the chip is set in Power Down mode. In this mode all circuitry is completely turned off and the internal clock is disabled. Hence, only leakage current contributes to the Power Down Dissipation. The startup time from this mode is longer than for other idle modes as all references need to settle to their final values before normal operation can resume. The SLP_N bus can be used to power down each channel independently, or to set the full chip in Sleep Mode. In this mode internal clocking is disabled, but some low bandwidth circuitry is kept on to allow for a short startup time. However, Sleep Mode represents a significant reduction in supply current, and it can be used to save power even for short idle periods. The input clock should be kept running in all idle modes. However, even lower power dissipation is possible in Power Down mode if the input clock is stopped. In this case it is important to start the input clock prior to enabling active mode.
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Digital Outputs
Digital output data are presented on parallel CMOS form. The voltage on the OVDD pin set the levels of the CMOS outputs. The output drivers are dimensioned to drive a wide range of loads for OVDD above 2.25V, but it is recommended to minimize the load to ensure as low transient switching currents and resulting noise as possible. In applications with a large fanout or large capacitive loads, it is recommended to add external buffers located close to the ADC chip. The timing is described in the Timing Diagram section. Note that the load or equivalent delay on CLK_EXT always should be lower than the load on data outputs to ensure sufficient timing margins. The digital outputs can be set in tristate mode by setting the OE_N signal high.
(c)2009 CADEKA Microcircuits LLC
Rev 2B
13
Data Sheet
Table 1: Data Format Description for 2Vpp Full Scale Range
Differential Input Voltage (IPx - INx) Output data: Dx_9 : Dx_0
(DFRMT = 0, offset binary)
Output Data: Dx_9 : Dx_0
(DFRMT = 1, 2's complement)
1.0 V +0.24mV -0.24mV -1.0V
11 1111 1111 10 0000 0000 01 1111 1111 00 0000 0000
01 1111 1111 00 0000 0000 11 1111 1111 10 0000 0000
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
Mechanical Dimensions
QFN-64 Package
aaa C A A D D1 aaa C B ccc C A A2 A3 A1
Symbol A A1 A2 A3 b D D1 D2 E E1 E2 F G L e Min - 0.00 - 0.008 Inches Millimeters Typ Max Min Typ - 0.035 - - 0.0004 0.002 0.00 0.01 0.026 0.028 - 0.65 0.008 REF 0.2 REF 0.010 0.012 0.2 0.25 0.354 BSC 9.00 BSC 0.354 BSC 8.75 BSC 0.205 0.213 5.0 5.2 0.354 BSC 9.00 BSC 0.344 BSC 8.75 BSC 0.205 0.213 5.0 5.2 - - 1.3 - 0.0168 0.024 0.24 0.42 0.016 0.020 0.3 0.4 0.020 BSC 0.50 BSC - 12 0 - Tolerance of Form and Position 0.10 0.004 0.10 0.004 0.05 0.002 Max 0.9 0.05 0.7 0.30
0.197
5.4
0.197 0.05 0.0096 0.012 0
5.4 - 0.6 0.5 12
E
E1
1
aaa bbb ccc
Pin 1 ID 0.05 Dia. 1 bbb C A C seating plane
NOTES:
1. All dimensions are in millimeters. 2. Die thickness allowable is 0.305mm maximum (.012 inches maximum) 3. Dimensioning & tolerances conform to ASME y14.5m. -1994. 4. Dimension applies to plated terminal and is measured between 0.20 and 0.25mm from terminal tip. 5. The pin #1 identifier must be placed on the top surface of the package by using indentation mark or other feature of package body. 6. Exact shape and size of this feature is optional. 7. Package warpage max 0.08mm. 8. Applied for exposed pad and terminals. Exclude embedding part of exposed pad from measuring. 9. Applied only to terminals. 10. Package corners unless otherwise specipied are r0.1750.025mm.
bbb C B B 1.14
1.14
TOP VIEW
Pin 1 ID Dia. 0.20 0.45 D2 F
SIDE VIEW
G
Rev 2B
E2
L e b 0.10 M C A B L
BOTTOM VIEW
(c)2009 CADEKA Microcircuits LLC
www.cadeka.com
14
Data Sheet
Mechanical Dimensions (Continued)
TQFP-64 Package
Symbol A A1 A2 D D1 E E1 R2 R1
1 2 3
Min - 0.002 0.037
c L L1 S b e D2 E2 aaa bbb ccc ddd
0.003 0.003 0 0 11 11 0.004 0.018 0.008 0.007
Inches Typ - - 0.039 0.472 BSC 0.393 BSC 0.472 BSC 0.393 BSC - - 3.5 - 12 12 - 0.24 0.039 REF - 0.008 0.020 BSC 0.295 0.295 0.008 0.008 0.003 0.003
Max 0.047 0.006 0.041
Min - 0.05 0.95
0.008 - 7 - 13 13 0.008 0.030 - 0.011
0.08 0.08 0 0 11 11 0.09 0.45 0.20 0.17
Millimeters Typ - - 1.00 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC - - 3.5 - 12 12 0.20 0.75 1.00 REF - 0.20 0.520 BSC 7.50 7.50 0.20 0.20 0.08 0.08
Max 1.2 0.15 1.05
CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
0.20 - 7 - 13 13
- 0.27
TOP VIEW
SIDE VIEW
NOTES:
1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maxmum plastic body size dimensions including mold mismatch. 2. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. 3. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages.
DETAIL SIDE VIEW
Rev 2B
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2009 by CADEKA Microcircuits LLC. All rights reserved.
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